Wed
Apr 1
2015
Apr 1
2015
The CI20 bare-metal project
Running bare-metal code (most recent first):
- User space: venturing below kseg0 for the first time.
- Some quick notes on threading models: an all-theory post about the M:N thread model.
- When you say nothing at all: on eliminating inter-core communication.
- Dual cores: Enable multicore.
- CMake: Switch build system.
- Interrupt handling: Basic support for interrupts.
- The DDR odyssey, part 4: memtester: Finishing off RAM initialisation by testing it.
- The DDR odyssey, part 3: memory remapping: Exploring the mystery of the DREMAP registers.
- The DDR odyssey, part 2: getting it working: Auto-generates DDR initialisation code and runs a basic memory test (which passes)!
- The DDR odyssey, part 1: PLLs: Initialises the JZ4780's phase-locked loops to provide a clock signal for the CPU and RAM.
- Enabling the timer: Enables one of the timers on the JZ4780.
- Running code on the CI20 without uboot: Uses the boot ROM of the JZ4780 system-on-chip to run code over USB, rather than relying on the u-boot bootloader.
- Running bare-metal code on the CI20, part 2: This gets you to the point of loading software from the u-boot bootloader which blinks a LED.
- Running bare-metal code on the CI20, part 1: This covers setting up a toolchain for compilation.
Diversions:
- LLVM support: Notes on adding support for a new toolchain.
- The impact of caching on MIPS: A short diversion which uses the LED blinking program to demonstrate how important caching is to performance.
- A reset button for the CI20: talks about using a reset line broken out in the EJTAG connector to construct a reset button.